ddr3 memory configuration....

[ijstokes-/2FeUQLD3jedFdvTe/nMLpVzexx5G7lz at public.gmane.org (Ian Stokes-Rees)]

   This didn't send properly, but Peter already pointed out the Dell article.
   My comments (copied below) may be relevant if you want to know what I got
   out of it.
   Ian
   On 10/20/10 11:11 AM, Ian Stokes-Rees wrote:

 I would take a look at this:

[1]http://www.delltechcenter.com/page/04-08-2009+-+Nehalem+and+Memory+Configura
tions

The memory controller is now on the CPU in 5500 series processors.

If you just want my interpretation, the short story is:

* buy on a per-processor (chip) basis
* buy in sets of 3 for maximum bandwidth/speed
* populate per-channel, rather than per-bank
* fill as few banks as possible (signal speed drop with each additional
bank, even if only partly filled)
* keep memory uniform on a per-bank basis (e.g. bank 1 has 3x4 GB, bank
2 has 3x2 GB for 18 GB total, each channel has 1x4GB (bank1)and 1x2GB
(bank2)), and ideally keep all DIMMs identical.

If you have a 2-processor system, then you are going to be buying RAM in
blocks of 6.  Fastest configuration will be to buy only 6 DIMMs, but
DIMMs get expensive past 4GB/stick, so if you need more than 24 GB,
you'll pay a premium

Ian

--
Ian Stokes-Rees, PhD                       W: [2]http://hkl.hms.harvard.edu
[3]ijstokes-/2FeUQLD3jedFdvTe/nMLpVzexx5G7lz at public.gmane.org               T: +1 617 432-5608 x75
NEBioGrid, Harvard Medical School          C: +1 617 331-5993

References

   1. http://www.delltechcenter.com/page/04-08-2009+-+Nehalem+and+Memory+Configurations
   2. http://hkl.hms.harvard.edu/
   3. mailto:ijstokes-/2FeUQLD3jedFdvTe/nMLpVzexx5G7lz at public.gmane.org