Makefile help needed

[bnorth at mindspring.com (B North)]

David Kramer wrote:
> >My problem is this:  I want to build a .o in a different directory from the 
> >current one, and it's being rather stubborn unless I spell out the rule.

That has always been my experience, that Make won't build "elsewhere"
unless you explicitly tell it to. This is probably a feature, so
it doesn't go fill up /usr/include with object files when you
screw up the dependencies in your Makefile :-)

So I think you need the second, spelled-out rule. If you want
to avoid duplicating the rule, you can do something like:

---snip---
COMPILE_RULE=$(CC) $(CFLAGS) -c $< -o $@
.c.o:
	$(COMPILE_RULE)
../otherdir/%.o : %.c
	$(COMPILE_RULE)

all: target1.o ../otherdir/target2.o
---snip---

Jim Van Zandt wrote:
> I suggest you try setting VPATH to point to the directory with the
> source file.

I think VPATH is only good for locating pre-requisites, it won't
make any difference for the target part of David's original
rule.

That said, you could invert the problem by forcing Make to
build "otherdir" targets by recursing into "otherdir" and 
using VPATH to find pre-reqs back in "thisdir":

---snip---
.c.o:
	$(CC) $(CFLAGS) -c $< -o $@
vpath %.c ../thisdir
../otherdir/%.o : %.c
	cd ../otherdir && $(MAKE) -f ../thisdir/Makefile $(@F)

all: target1.o ../otherdir/target2.o
---snip---

You still have the extra rule, but it no longer duplicates
the compile details. This seems to work (GNU Make 3.80). 
Recursive Makefiles, though, have their own pitfalls. 

Ben
Full disclosure: In a previous job, I had something of a reputation 
for creating "write-only" Makefiles, so maybe you really
don't want my advice :-)