AMD-V: AMD64 virtualization extension

Date and Time

Wednesday, November 18, 2009 from 6:30 pm to 9:00 pm

Location

MIT Building E-51, Room 325

Presenters

Shankar Viswanathan , AMD Semiconductor - shankar.viswan gmail com

Summary

Shankar discusses AMD's hardware virtualization

Abstract

Shankar Viswanathan will describe the details of the hardware virtualization features implemented in AMD64 processors. Named AMD-V (formerly codenamed "Pacifica"), these architecture extensions greatly reduce the overhead involved in running multiple guest operating systems on top of the Virtual Machine Monitor (VMM). Shankar will discuss how AMD-V handles tasks such as saving and restoring OS state, how memory and paging is handled and give a brief overview of how IO peripherals are virtualized. A rough knowledge of the x86 architecture is beneficial, but not a prerequisite for this talk.

Bio

Shankar Viswanathan is the lead performance architect for AMD's Strategic Silicon products. He has worked on the design and verification of several generations of AMD processors. Most recently, he was on the design team for the SoCs that power game consoles such as the PlayStation5 and the Steam Deck. His general interests like at the intersection of performance and security in hardware platforms.