Short Takes: CXL in High Performance Computing; SCC Redux; and the UCIe Standard for Chip Design
Date and Time
Wednesday, October 18, 2023 from 6:30 pm to 9:30 pm
Kurt Keville , Thaumaturgical Engineer , MIT Clinical Research Center - kkeville alum mit edu
Shankar Viswanathan , AMD Semiconductor - shankar.viswan gmail com
New developments in HPC and Chip Design, and various projects from the 2023 Student Cluster Competition
There are new hardware processes and programming paradigms that promise to dramatically improve process yields and performance. CXL will unlock academic research computing disciplines that currently have no solution path. These include deeply recursive codes and
applications that require large memory blocks.
Unified Acceleration (UXL), was announced last month at the Linux Foundation Open Source Summit with the goal of delivering a multi-architecture and multi-vendor software ecosystem for all accelerators based on open source standards. And Universal Chiplet Interconnect Express (UCIe) is helping to build an open ecosystem of chiplets for on-package
Shankar Viswanathan is the lead performance architect for AMD's Strategic Silicon products. He has worked on the design and verification of several generations of AMD processors. Most recently, he was on the design team for the SoCs that power game consoles such as the PlayStation5 and the Steam Deck. His general interests like at the intersection of performance and security in hardware platforms.