[Discuss] AMD FX-8120 update

[shankar.viswan at gmail.com (Shankar Viswanathan)]

On Mon, Mar 5, 2012 at 11:53 PM, Bill Ricker <bill.n1vux at gmail.com> wrote:
>> I'd be happy to explain the high-level details of the architecture to
>> anyone that cares.
>
>
> So is the Northbridge effectively half on-die and half off-chip ?

Yes: slide #28 illustrates this to some extent. The "Valencia" die has
the part of the northbridge with the crossbar, L3 cache and the DRAM
controller. The SR56x0 "Northbridge expansion I/O" chip contains the
I/O controller and the PCIe I/O lanes (among a few other things). The
Valencia die and the SR56x0 are connected via a HyperTransport link.

Slide #28 is for a 2-socket server configuration -- for a single
processor desktop or server, there will obviously be only processor
one die at the top and the part numbers for the expansion Northbridge
and Southbridge may vary.

When we get to the upcoming AMD Fusion APUs for desktops and laptops
based on the Bulldozer core architecture (punch in 'AMD Trinity' into
your favourite search engine), the story is obviously different. The
entire Northbridge, i.e. both the memory controller part *and* the I/O
part, will be on the same die, along with the Bulldozer modules and an
AMD Radeon HD graphics controller. There are a few other differences
that I probably can't talk about yet :-)

-Shankar